A multiple-row transistor placement system for full custom design


This paper presents a multiple-row transistor placement system for full custom design. The system is flexible in supporting a wide variety of process technologies and a range of library template styles. This automatic transistor placer provides many options for users to customize their layouts. Transistor folding, transistor pairing, transistor chaining, row partitioning, and transistor placement are integrated into this system for the generation of high-performance, dense, design-rule correct layouts. In addition, a high level stick diagram, enabling gate swapping, splitting and merging gives layout designers the ability to perform manual optimization without the need to prepare different sizes of gate transistors for supporting these device manipulations. Experimental results indicate that the automatic generated transistor layouts are competitive with manually designed layouts in terms of execution time and the numbers of diffusion breaks.


7 Figures and Tables

Download Full PDF Version (Non-Commercial Use)